Jump to content
Sign in to follow this  

Generic covergroups and constraints

Recommended Posts


I have a question concerning covergroups and constrains in SystemVerilog.

I would like to make them generic, depending on parameters. For example, if there is a SIGNAL_WIDTH parameter, i'd like my covergroup to have bins like {0}, {2^SIGNAL_WIDTH - 1}.

The same about constraints, let's say i want to constrain a value to 2^SIGNAL_WIDTH - 1.

We are verifying DUT which are parametrizable; this is needed so we don't have to re-write the UVM classes when changing the parameter.

Moreover, if there is a NB_VALUES parameter (or constant), is there some kind of "generate" (as in verilog and vhdl) feature to generate a constraint for each of these values?

Edited by laurent.elsys

Share this post

Link to post
Share on other sites

Your classes can be parameterized using the same parameters as your DUT. It would be great if both DUT and testbench can share a set parameters defined in the same package.

Edited by dave_59

Share this post

Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now
Sign in to follow this