qwerty Posted November 19, 2012 Report Share Posted November 19, 2012 (edited) Hi, I am instantiating a sequence in another sequence and i have made it parametrized. but i am getting a invalid cast error at run time. class a_seq: class a_seq extends base_seq `uvm_object_utils(a_seq) function new(string name="a_seq"); super.new(name); endfunction `uvm_object_utils(a_seq) b_seq #(12) s0; task body(); `uvm_do(s0) endtask endclass class b_seq: class b_seq #(parameter bit [16:0] address = 0) extends base_seq `uvm_object_utils(b_seq) task body(); final_addr=addr_calc(addres); `uvm_do_with(req,{req.addr== final_addr}) endtask endclass error: `uvm_do(s0) | ncsim: *E,BCLCST (../src/sv/seq_lib.sv,226|16): Invalid cast: a value with the class datatype 'tb_top.intR_rd_seq#(17'h00000)' cannot be assigned to a class variable with the datatype 'tb_top.intR_rd_seq#(17'h0000c)'. Edited November 19, 2012 by qwerty Quote Link to comment Share on other sites More sharing options...
uwes Posted November 19, 2012 Report Share Posted November 19, 2012 did you miss the `uvm_object_param_utils(b_seq#(address)) ? not sure since essential parts of the code are missing and the error msg is incomplete Quote Link to comment Share on other sites More sharing options...
qwerty Posted November 19, 2012 Author Report Share Posted November 19, 2012 Thanks Uwes, `uvm_object_param_utils(b_seq#(address)) but now i am getting a FATAl error. UVM_FATAL @ 322500: uvm_test_top.tb.m0.ag.sequencer [sequencer] send_request failed to cast sequence item Quote Link to comment Share on other sites More sharing options...
uwes Posted November 20, 2012 Report Share Posted November 20, 2012 can your sequencer handle b_seq#(12) sequences? it sounds to me as if you did not fully supply the parameter in all the places. my assumption would be that you have somewhere an assignment of a b_seq#(0) to a b_seq#(12). i would check for places where b_seq is used without parameter. Quote Link to comment Share on other sites More sharing options...
qwerty Posted November 20, 2012 Author Report Share Posted November 20, 2012 It was because of wrong handle to the sequencer. One more thing, the Virtual sequencer by default randomly pics a sequencer of execute its sequences. but if we want to use the sequencer in a specific order then is grab/ungrab the way to do it? Quote Link to comment Share on other sites More sharing options...
joniale Posted October 22, 2015 Report Share Posted October 22, 2015 Just to put it clearly you cannot change the parameters dynamically. That would not work. That is to say Your address in: class b_seq #(parameter bit [16:0] address = 0) extends base_seq need to be a constant or static not changing in the run_phase. In other words, a virtual sequencer or the task that will start this sequence cannot use a variable for this. If you want to pass info between seq classes you can just create rand class variables and set them with randomize with before you execute the sequence. you can also use `uvm_do_on_with(xfer_or_seq,sequencer {address==32'hABCD}); The following info should help https://verificationacademy.com/cookbook/sequences/generation Quote Link to comment Share on other sites More sharing options...
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