Jump to content
Sign in to follow this  
sanketshah

Semaphore/uvm port

Recommended Posts

>Can we use semaphore in Systemverilog function?

depends what you mean. you can instantiate it in a function, call put(),try_get() BUT you cant directly invoke get() since this could block if there are insufficient keys avail. and since you are in a function you cant have anything blocking in there.

>Can we call put and get implementation task from the function in UVM?

what do you mean TLM/semaphore or something else?

Share this post


Link to post
Share on other sites

>Can we use semaphore in Systemverilog function?

depends what you mean. you can instantiate it in a function, call put(),try_get() BUT you cant directly invoke get() since this could block if there are insufficient keys avail. and since you are in a function you cant have anything blocking in there.

>Got it.

>Can we call put and get implementation task from the function in UVM?

what do you mean TLM/semaphore or something else?

> I have three analysis ports and for that I have implemented three write functions in a class. Now I want to share a resource among this functions. One way I thought is to use semaphore, but we can only use it in task or any other procedural block but analysis implements write function not task. The other way I can think of is to implement own analysis port and implementation port where I can code my own write task instead using inbuilt write function. Is there any other way that I can share piece of code among write functions?

Share this post


Link to post
Share on other sites

You are going to have to explain a little more about the resource you want to share. The analysis port write methods are functions and therefore cannot be active concurrently.

Perhaps you meant to use three analysis fifos and have the subscriber class arbitrate which fifos it does a get() from.

Share this post


Link to post
Share on other sites

Lets say, I have three monitors and all of them have analysis port. Now I have only one component which implements this write functions. For example write_a, write_b, and write_c. Monitor1 one calls ap.write_a, Monitor2 calls ap.write_b, and Monitor3 calls ap.write_c. According to new UVM feature, We can have multiple write functions. Each monitor may call their respective functions as they observe the transaction, which happens randomly. Now I want to send only one of this at a time to upper layer if they all arrive at the same time. Because I have some priority issue among this transactions. So I want to implement semaphore among this functions. Basically, I want to implement inter process communication among functions which is not possible.

Let me know if you have further questions.

Share this post


Link to post
Share on other sites

I have to use write functions because My each monitor broadcasts the same information to its scoreboard. What is the use of implementing analysis fifos? I do not know how to arbitrate by peeking into each FIFO and selecting them using get from FIFO. Can you elaborate on that please?

Share this post


Link to post
Share on other sites

try_put() is a function that returns true if the put succeeds, which is always the case for an unbounded mailbox. That is exactly what an analysis_fifo is. You can have multiple subscribers on one analysis port. One subscriber would be the scoreboard, and the other is this component that you seem to require. Look at the code for the uvm_in_order_comparator.

Share this post


Link to post
Share on other sites

Hey Dave,

Means, I will have to implement try_put method inside my receiving class. What happens if all write_() functions calls this method at the same time? Means write_a, write_b and write_c calls try_put method at the same time.

Share this post


Link to post
Share on other sites

No, use the run_phase in your receiving class.

class receiving_class extends uvm_component;
  uvm_tlm_analysis_fifo #(T) a_fifo;
  uvm_tlm_analysis_fifo #(T) b_fifo;
  uvm_tlm_analysis_fifo #(T) c_fifo;

  uvm_blocking_put_port #(T) up_level_port;

  task run_phase(uvm_phase phase);
  T a,b,c;
  forever begin
         fork
              a_fifo.get(a);
              b_fifo.get(;
              c_fifo.get(c);
         join
        // figure out what you want to do with a, b, or c
       ....
       up_level_port.put(a_or_b_or_c);
       end
endtask
endclass
This is essentially what is inside the uvm_in_order_comparator. Edited by dave_59
up_level_port correction

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now
Sign in to follow this  

×