Can a instance of Interface be used in a virtual sequence?

[paragsathe]

Methodology wise, is it permissible to use an instance of virtual interface in a virtual sequence for peeking into status signals or enable signals to take the data transfer forward?

[uwes]

hi,

typically you should NOT peek/poke directly from the transaction layer into the physical/bit layer. this is not a good solution for reuse and scalability.

btw: if you know and accept the downsides it might be the coding wise faster solution.

/uwe

[paragsathe]

But suppose i need the status of a particluar signal to cal a sequence inside a virtual sequencer, is there a way other than peek/poke the interface signals.

[Erling]

>But suppose i need the status of a particluar signal to cal a sequence inside a virtual sequencer, is there a way other than peek/poke the interface signals.

Yes, the interface signals can be abstracted away. The status needed can be given a name, and providing that named status can be put as a requirement on the top level environment, i.e. simply assert that a testbench for my_dut shall provide status this and status that. When the test, in turn, is implemented by means of the testbench, it can just ask the testbench for status between sequences as needed, without direct reference to interface signals. Virtual sequences too can be implemented by means of the testbench, and can get hold of status in the same way a test would do. In this way, the testbench can use whatever method it likes to obtain the status, e.g. receive it through a port or event, or forward the status request to a component in the interface. The test or virtual sequence wouldn't notice the difference.

Erling