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Generating unique addresses for a write sequence


ssingh

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Try reading about randc in systemverilog documentation.

I never had to use, but I guess you could use something like:

<inside sequence class>

randc bit [7:0] address;

virtual task body();

<loop>

void'(this.randomize());

`uvm_do_with(req, {req.addr == address;})

</loop>

...

the randc generates a random value sequence without repeating any value. After all possible values are met, it generates a new random sequence.

Edited by whiteriver
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to the limitation 1: then, what about using the randc as a seed to each value generated? it would be something like:

<inside sequence class>

randc bit [15:0] addr_seed;

bit [31:0] addr_to_send;

virtual task body();

<loop>

void'(this.randomize());

addr_to_send = $random(addr_seed);

`uvm_do_with(req, {req.addr == addr_to_send;})

</loop>

...

it will generate 32-bit values, the only implication is that it is limited to 2^16 possible values. Which brings to your second statement. I don't know how to solve it. But you can hack and create a sequence of seeds:

int seeds = 0;

<outer repeat loop>

<inner repeat loop 2^16 -1 times>

addr_to_send = $random((addr_seed<<16*seeds));

`uvm_do_with...

</inner repeat>

seeds+1;

</outer repeat>

which then has the limitation of 2^17 possible values (2x outer loop).

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I don't want to be limited to 2^16 possible values. I got one more possible solution on another forum:

You can have a queue of addresses that you have written to, and have a constraint

rand unint64 address;

uint64 list[$];

constraint not_in_list {!(address inside {list};}

function void post_randomize()

list.push_back(address);

endfunction

Thank you for your suggestion.

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