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drianf0

error injection

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Hello,

I would like to ask whether the reference design exits which would introduce an error injection and would present a methodology how to handle it. I am acquainted with the basic examples like the UBUS, APB and UVM_ref_flow_1.1 (Cadence's contribution). However, all of them, I understand for simplicity, work on transaction level, where a driver sends a content of a sequence_item in the proper way. In my case, I would like to add the error injection on low level. For example, in case of a SERDES, it could be a simple introduction of disparity errors, wrong codding, ect. Is any design pattern defined to add such a functionality in the UVM ?

I have tried to obtain it with inheritance. However --- I had to override a driver, monitor, sequences, ect... Basically, a reasonable part of the whole testbench. Moreover, developing the new functionality(error injection) I had to quite often modify base classes, which shouldn't happen in well designed class scheme. I would be grateful for any remarks/thoughts/examples.

Regards,

Adrian

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I don't think it needs to be that complicated. I think there are many ways to do error injection and detection. You can define some error fields as random variables within your sequence item. Then, design your driver to check the error field(s) settings, and drive an erroneous transaction on the bus accordingly. On the other side, you can design your monitor to detect bus-level errors, and set the appropriate error field(s) in the sequence item put together there before broadcasting to the analysis domain. I would just add the error-related functionality directly into your driver, monitor, and sequence item. The way I see it, errors are a basic attribute of any protocol. I'm not sure what you were trying to do with inheritance, but subclassing error-aware components from error-ignorant components seem unnecessary.

Hello,

I would like to ask whether the reference design exits which would introduce an error injection and would present a methodology how to handle it. I am acquainted with the basic examples like the UBUS, APB and UVM_ref_flow_1.1 (Cadence's contribution). However, all of them, I understand for simplicity, work on transaction level, where a driver sends a content of a sequence_item in the proper way. In my case, I would like to add the error injection on low level. For example, in case of a SERDES, it could be a simple introduction of disparity errors, wrong codding, ect. Is any design pattern defined to add such a functionality in the UVM ?

I have tried to obtain it with inheritance. However --- I had to override a driver, monitor, sequences, ect... Basically, a reasonable part of the whole testbench. Moreover, developing the new functionality(error injection) I had to quite often modify base classes, which shouldn't happen in well designed class scheme. I would be grateful for any remarks/thoughts/examples.

Regards,

Adrian

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