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raghavendrap

usage of build-in reset register sequence

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Hello all,

I am trying to up the built-in reset register sequence in my environment.

The problem is , in adapter bus2reg is not updating the mirrored value read from the DUT.

Here, i am using auto-prediction,

any suggestions how to overcome the problem.

Thanks

Raghavendra

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You probably mean the "hardware reset register test" sequencer.

There normally wouldn't be a need to update the mirrored value as the registers are supposed to contain their reset values -- which is already reflected in the register model (you did call uvm_reg_block::reset() on your model first, right?).

Many things can go wrong and you have not provided enough information to determine the likely source of the problem. I recommend asking an experienced user in your company or your vendor support team to help as working on the actual example to diagnose the problem is often necessary in these cases.

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Hello Janick,

I am seeing below error message in my log

UVM_INFO @ 34000: reporter [RegModel] Read register via map regmodel.uvm_reg_map: regmodel.XXX_APRB_CTL=0

UVM_ERROR /tools/synopsys/2011.12-SP1/etc/uvm/src/reg/uvm_reg.svh(2906) @ 34000: reporter [RegModel] Register "regmodel.XXX_APRB_CTL" value read from DUT (0x0000) does not match mirrored value (0x03f9)

But i am seeing reset value on the bus correctly, which i captured through monitor

UVM_INFO ../env/xxx_master_monitor.sv(64) @ 34000: uvm_test_top.xxx_config_tb0.xxx0.master[0].monitor [XXX_MASTER_MONITOR] -------------------------------------------------

Name Type Size Value

-------------------------------------------------

item xxx_master_transaction - @822

rd rw_e 32 READ

status status_e 32 IS_OK

data integral 16 'h19

addr integral 8 'h1

-------------------------------------------------

But when i print bus2reg item i am not seeing the value .

UVM_INFO ../env/ral_single.sv(65) @ 34000: reporter [reg2tr] bus2reg information...

-----------------------------------------------------------------------------------------------------------------

Name Type Size Value

-----------------------------------------------------------------------------------------------------------------

tr xxx_master_transaction - @817

rd rw_e 32 READ

status status_e 32 IS_OK

data integral 16 'h0

addr integral 8 'h1

begin_time time 64 30000

end_time time 64 34000

depth int 32 'd2

parent sequence (name) string 20 uvm_reg_hw_reset_seq

parent sequence (full name) string 20 uvm_reg_hw_reset_seq

sequencer string 52 uvm_test_top.xxx_config_tb0.xxx0.master[0].sequencer

-----------------------------------------------------------------------------------------------------------------

These are the steps i followed.

1) Generated REGMODEL from ralgen

2) Integrated into my environment

4) created adapter class and register sequence extending from uvm_reg_sequence

3) connected default bus sequencer to regmodel

In my testcase i am starting hardware reset sequence like below:

uvm_reg_hw_reset_seq reg_reset_seq;

reg_reset_seq.model = xxx_config_tb0.xxx0.regmodel;

reg_reset_seq.start(null); // assuming the default sequencer has been set up for the frontdoor

Thanks

Raghavendra

You probably mean the "hardware reset register test" sequencer.

There normally wouldn't be a need to update the mirrored value as the registers are supposed to contain their reset values -- which is already reflected in the register model (you did call uvm_reg_block::reset() on your model first, right?).

Many things can go wrong and you have not provided enough information to determine the likely source of the problem. I recommend asking an experienced user in your company or your vendor support team to help as working on the actual example to diagnose the problem is often necessary in these cases.

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Hello Janick,

Here is my adapter class:

class reg2tr extends uvm_reg_adapter;

`uvm_object_utils(reg2tr)

function new (string name="reg2tr");

super.new(name);

endfunction

virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);

xxx_master_transaction tr;

tr = xxx_master_transaction::type_id::create("tr");

tr.rd = (rw.kind == UVM_READ) ? xxx_master_transaction::READ : xxx_master_transaction::WRITE;

tr.addr = rw.addr;

tr.data = rw.data;

`uvm_info(get_type_name(),$sformatf("reg2bus information...\n%s", tr.sprint()), UVM_LOW)

return tr;

endfunction

virtual function void bus2reg (uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);

xxx_master_transaction tr;

if (!$cast(tr, bus_item)) begin

`uvm_fatal("NOT_xxX_TYPE","Provided bus_item is not of the correct type")

return;

end

rw.kind = tr.rd ? UVM_READ:UVM_WRITE ;

rw.addr = tr.addr;

rw.data = tr.data;

rw.status = UVM_IS_OK;

`uvm_info(get_type_name(),$sformatf("bus2reg information...\n%s", tr.sprint()), UVM_LOW)

endfunction

endclass: reg2tr

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I resolved this problem.

response is not proper from driver to sequencer, that's y i am not able to see read data path .

--Raghavendra

Hi Rag,

I have encountered the same issue. How did you see the response from driver to sequencer successfully? Could you give me any suggestion?

Thanks in advance.

mrforever

Edited by mrforever

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