SeanChou 1 Report post Posted June 28, 2012 Hi simulator exports, UVM already helps a lot to make our TB works with multiple simulators. however, this makes us found some existed RTL is eval order dependent. which cause the simulation results are wrong if we changed the simulators. Theretically we could fix it after which is found. however, designer depends and not willing to fix since the RTL is already silicon proven. so this confusing us a lot. Is there any static or more systematic way to make our DUT eval order independent? Thanks a lot in advanced! Share this post Link to post Share on other sites
uwes 17 Report post Posted June 28, 2012 hi, this is more a "design methodology / rules" question. there are safe design rules which basically ensure that you dont have race conditions, your rtl behaves like the synth netlist, you are not using "grey" LRM constructs/semantic,... Since these are lots of rules people typically use design-rule checker, linter etc. you may even run on different simulators to spot suspicious behavior and see if simA and simB have a common understanding of what you described. /uwe Share this post Link to post Share on other sites
adielkhan 0 Report post Posted June 28, 2012 hi, there are many papers on this topic the one I refer to most often is BSNUG2006 SystemVerilog Event Regions, Race Avoidance & Guidelines by Arturo Salz and Cliff Cummings. http://www.synopsys.com/news/pubs/snug/boston2006/cummings_paper.pdf Slide 6 is most informative. 6 years later the LRM has moved on a little but the basic principles still hold. Of course a good Lint tool would add automation and make code-reviews much less painful. -adiel. Share this post Link to post Share on other sites
