UVM_ANALYSIS port in sequence

[bverma 0]

Can I declare a uvm_analysis port in sequence ?

I get message like

Error-[iCTTFC] Incompatible complex type usage

/tools/eda/VCS/vF-2011.12/etc/uvm-1.1/tlm1/uvm_analysis_port.svh, 112

Incompatible complex type usage in task or function call.

The following expression is incompatible with the formal parameter of the

function. The type of the actual is 'class ....'

Thanks

[dave_59 34]

No, you cannot. All TLM ports must be connected before any sequences start.

You can put a port in the sequencer that you can reference from the sequence. I don't remember, but the sequencer may already have analysis ports that you can connect up that write out what is being sent to the driver.

[arno 2]

No, you cannot.

Actually you can.

On use example : to send the transfers generated by the sequence to a scoreboard.

[dave_59 34]

Yes, you can call the write method of an analysis port from a sequence that was declared in some other component class, but you can't declare the analysis port inside the sequence.

[bverma 0]

To call that write method, we need to declare an uvm_analysis_impl port. Is that correct.

I tried to declare an implementation port and I am getting this error

Error-[iCTTFC] Incompatible complex type usage

/tools/eda/VCS/vF-2011.12/etc/uvm-1.1/tlm1/uvm_analysis_port.svh, 112

Incompatible complex type usage in task or function call.

The following expression is incompatible with the formal parameter of the

function. The type of the actual is 'class

Thanks,