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UVM Connect Web Seminar

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UVM Connect Web Seminar

See go.mentor.com/uvm-cnx for more information on Mentor's UVM Connect web seminar and to register.

Date: 10 April 2012

Time: 8:00 AM - 9:00 AM US/Pacific (Convert to Local Time)

Overview

UVM Connect is a new open-source UVM-based library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog UVM models and components. UVM Connect allows you easily to develop integrated verification environments where you take advantage of the strengths of each language to maximize your verification productivity.

Anyone who wants to combine both SystemVerilog UVM and SystemC in a common verification environment should be using UVM Connect. This includes SystemC designers who want to leverage SystemVerilog UVM functionality to add functional coverage and constrained-random stimulus to their verification environment. It also includes SystemVerilog designers who want to use SystemC models as reference models in their environment or any other application that requires components of both languages to run together.

What You Will Learn

  • Review the principles of the TLM1 and TLM2 standards, including the basic port/export/interface connections in both SystemC and SystemVerilog
  • How to establish TLM-based connections between SystemC and SystemVerilog UVM components
  • How to write converters to transfer transaction data across the language boundary
  • How to wrap a SystemC reference model for use as a SystemVerilog UVM verification component
  • How to access and control key aspects of UVM simulation from SystemC

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