Mentor Graphics Drives Broader Adoption of UVM

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http://www.businesswire.com/news/home/20120222005387/en/Mentor-Graphics-Drives-Broader-Adoption-UVM

Mentor Graphics Drives Broader Adoption of UVM

WILSONVILLE, Ore., Feb. 22, 2012—Mentor Graphics Corporation (NASDAQ: MENT) today announced expanded support for the Universal Verification Methodology (UVM). The UVM delivers productivity gains made possible by reuse in functional verification. For verification teams with minimal exposure to UVM, the first step to implement a UVM-based verification environment is simply getting started. To facilitate that first step, Mentor introduces UVM Express, a way to progressively adopt a UVM methodology. Other verification teams have an established UVM-based verification environment, but are challenged to move their trusted verification approach up in abstraction where a new level of system verification can be achieved. For those verification teams, Mentor introduces UVM Connect, which provides standard TLM 1.0 and TLM 2.0 connectivity between models written in SystemC and UVM SystemVerilog.

“Mentor continues to see massive interest in UVM, and we are committed to leading the effort to make UVM an integral part of every functional verification flow,†said John Lenyo, vice president and general manager of the Design Verification Technology division at Mentor Graphics. “For verification teams using UVM for the first time, UVM Express makes getting started easy and intuitive, and extends rapid productivity gains to a broader scope of design projects. With UVM Connect, we’ve created a link between abstraction levels that enables design and verification engineers to take advantage of each level’s best features without sacrificing the ability to reuse work.â€

 

About UVM Express

Verification teams often have time and budget constraints that make adoption of new methodologies difficult. These teams are exactly the kind of teams that the UVM is meant to help, but the first step towards adoption is currently too high. UVM Express provides a way to build the testbench environment, a way to raise the abstraction level, a way to check the quality of tests and a way to think about writing tests. Each of the steps outlined for UVM Express is a reusable piece of verification infrastructure. These UVM Express steps are a way to progressively adopt a UVM methodology, while getting verification productivity and verification results at each step.

Using UVM Express is not a replacement for full UVM, but instead enables full UVM migration or co-existence at any time. UVM Express helps everyone, regardless of their experience level, to accelerate time to success.

About UVM Connect

As design teams move to higher levels of abstraction for system-level architectural exploration and definition, the need for efficient and reusable functional models becomes imperative. Design and verification teams work with a plethora of functional models sourced in different design languages, primarily SystemC and SystemVerilog, where the choice of language is made in order to exploit the advantages of the native language. By facilitating cross-language communication via standard transaction level modeling (TLM) interfaces, UVM Connect allows for the reuse of SystemC architectural models as reference models in SystemVerilog verification, and expands the inventory of Verification IP (VIP) by making it easier to integrate off-the-shelf VIP. It lets verification teams maximize productivity in a mixed-language, mixed-tool environment by using either SystemC or SystemVerilog to implement key pieces of their testbench and provides direct access to UVM state and control flow from outside SystemVerilog.

Availability

UVM Express and UVM Connect functionality is available immediately and can be downloaded from the Mentor Verification Academy website: http://verificationacademy.com/. Verification Academy modules on using UVM - UVM Express and UVM Advanced – as well as additional training material and online documentation are also available on the Verification Academy website.

About Mentor Graphics

Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues over the last 12 months of about $915 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.

Mentor Graphics and Mentor are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.