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paragsathe

Constaining register fields from the testcase

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If we are using a register layer in our UVM testbench, how to contrain the individual register fields from the testcase? Do we just do it using an object of the register model we have written?

can anyone throw some light on this?

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If we are using a register layer in our UVM testbench, how to contrain the individual register fields from the testcase? Do we just do it using an object of the register model we have written?

can anyone throw some light on this?

Commonly, we just create one uvm_object for all registers fields , and then do some constraints for each of them. In the specific phase, You will random some fields and write to DUT through Register layer in the UVM Tb.

If you need to test the functional features of DUT, you may use above.

If you want to test Register, you may use the build-in sequences for reset/random access.

Hope this to help you.

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if you are using RALF, you can add the constraints in the Input specifications (RALF itself), add constraints for the 'value' of different fields.. IPXACT1.5 also allows you to add constraints

You can also add inline constraints while randomizing individual fields, registers..

eg:model.regname.randomize() with ...

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If you are using Cadence RGM Pkg, you could try following codes in you TB

// Block-level sequence : This sequence is meant to work for 'block_rf'

// type container. All registers are accessed relative to 'block_rf'

// container

class block_seq extends uvm_rgm_sequence;

reg_t r;

virtual task body();

if(!container) container=p_sequencer.get_container();

p_sequencer.uvm_report_info(get_name(),

$psprintf("Seq Starting. Container = %s", container.get_full_name()));

$cast(r, get_reg_by_name("urf.uart_reg0"));

void'(r.randomize() with {value=='h12345678;});

`rgm_write_send®

....

endclass

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