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UVM assert(req.randomize(clkgen) with {clock.period ==period ;}); doesn't work in VCS

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Hi ,

I am using UVM 1.0 from Accellera and VCS vcs-mx-E-2011.03.

In my sequence, I have the following syntax

assert(req.randomize(clkgen) with {clock.period ==m_period ;});

However, I see print out m_period is correct ( a non zero number) but clock.period in item req is zero.

I have a timescale directives in uvm_users_pkg as timescale 1ns/1ps, but I use +override_timescale 1ps/1ps as VCS_OPT

this syntax works fine with mti, but doesn't work in VCS. and because this is a clock generator, all the clock has period as "zero" , and VCS stops because it detected infinite loop (of course).

Anyone has experience on this?



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Hi Bin,

Please can you supply some more information.

The code you have written states you are randomize req.clkgen and are checking that req.clock.period == req.m_period. No randomization of clock.period or m_period will occur.

Is this your intention, I suspect it is not ?

Please modify testcase to show what you are trying to do.

program prog;
class clk;
   rand int period =1;

class foo;
  rand clk clock;
  rand int clkgen;
  rand int m_period = 1;
  function new();
     clock = new();      

  foo req;

  initial begin
     assert(req.clock.period ==req.m_period) 
assert(req.randomize(clkgen)) $info ("\n Randomization passed \n") ;
        else $error("\n Randomization failed \n");   
      else $error("values are not equal before randomization");




Edited by adielkhan

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