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saad

One clock cycle delay in communication between two SC_CTHREAD

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I am trying to model a direct mapped cache and there is main memory module which is an SC_CTHREAD and main memory state machine which also SC_CTHREAD. I am experiencing one clock cycle delay when I write to an output from main memory and read it from main memory state machine. But i thought i could read in the same clock cycle isnt it true?

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Thank you very much for your helpful answer.

Now I am trying to use SC_THREAD but confuse in one thing that how can I model a register in SC_THREAD. Because I know that if we declare a variable in SC_CTHREAD as sc_signal than it is modeled as a register but how can I do that in SC_THREAD. I can make SC_THREAD sensitive to a positive clock edge and a reset but I do not think that will model the registers where I want them.

 

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11 minutes ago, saad said:

I can make SC_THREAD sensitive to a positive clock edge and a reset but I do not think that will model the registers where I want them.

What do you mean exactly by "modeling a register"?

If you are working on synthesizable code (i.e. using Mentor/Cadence HLS tools), then it is not possible to have 0-delay communication between threads in synthesizable code, as you wanted in original post. At least it was not possible last time I've used these tools. 

If you are working on some non-synthesizable high-level model, then you can model "register" any way you like, you don't even have to use sc_signal<> for that purpose. 

 

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I mean like an output register which can save a value for one clock cycle and than put the value on its output if the enable signal is high.

and what do you mean by we can model a register in anyway we want? or do you mean if I make SC_THREAD sensitive to clock pos edge and than get an enable signal as an input to SC_THREAD and make an if condition if enable signal is high output = input than it will behave like a register and yes I am working with non-synthesizable high level model and just running systemC from command line as presented in forte design system series on youtube.

 

Edited by saad

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You have controversial requirements:

a) put stored value when enable == 1 , which sounds like a dff with output_enable 

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output register which can save a value for one clock cycle and than put the value on its output if the enable signal is high.

b) put input to output when enable == 1, which sounds more like a latch

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if enable signal is high output = input

Anyway, in both cases you will need to make process sensitive to enable signal. And usually such  low-level logic is modeled with SC_METHODs.

In SystemC context "register" usually means some memory-mapped CSR on TLM bus 🙂   

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Hi,

I am now trying to use SC_Methods but having some problem in running multiple SC_methods within one SC_module. Is it possible to have multiple SC_METHODs in one SC_MODULE? problem solved

 

Edited by saad
solved

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