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Khushi

How to develop a cycle accurate model in systemc

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Establish a clock period and insert appropriate wait( N*period ) as needed.

Cycle accurate is seldom actually required, and cycle approximate is more likely.

For instance, if you know that read transactions on a bus take 2 clocks and you make 5 accesses, you can lump that into a single 2 * 5 * period delay.

 

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Thanks David

I have few connected questions

There are lot of people talk about cycle accurate models to speed up the simulation. What are those cycle accurate models? Are those written in SystemC ? If not can you explain a bit on this.

Can we connect an untimed tlm model to a rtl block and simulate it seamlessly.

Do we need to take care few things in untimed tlm model to make it work in a cosimu environment?

I remember someone implementing a SystemC model with individual axi pins as sc_bv/sc_lv types instead of using the tlm2 socket. What are the usage of such models?

Suppose I connect a tlm2 socket to a rtl axi interface using some adapter eg tlm2axi, in this case do we need cycle accurate or approximate model on tlm side for a smooth operation.

 

Thank

khushi

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Quote

There are lot of people talk about cycle accurate models to speed up the simulation. What are those cycle accurate models? Are those written in SystemC ? If not can you explain a bit on this.

Probably you talk about cycle-based simulators? Like for example Verilator (https://www.veripool.org/wiki/verilator).  Cycle-based simulators are faster than discrete-event simulators if you have a cycle-accurate model like RTL. Also cycle-based simulation is easier to parallelize.

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 I remember someone implementing a SystemC model with individual axi pins as sc_bv/sc_lv types instead of using the tlm2 socket. What are the usage of such models?

Oftern pin-level interfaces are used to integrate some RTL into C++ simulators.  Or opposite, integrate high-level C++ simulators into RTL verification environment. Commercial simulators like VCS can automatically generate SystemC pin-level wrapper for Verilog, or Verilog wrapper for SystemC. Then you can do cosimulation.  

Another usage for pin-level interfaces is High-Level Synthesis. HLS tools from Cadence and Mentor take SystemC models with pin-level interfaces as an input.

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At https://git.minres.com/DVCon2018/RISCV-VP/src/branch/develop/platform/src/rtl and https://git.minres.com/DVCon2018/RISCV-VP/src/branch/develop/platform/incl/sysc/rtl you may find some example of an integration of a cycle-based model (Verilator+Verilog RTL) into a VP using LT-style modelling. This is from last-years DVCon Europe (http://events.dvcon.org/events/proceedings.aspx?id=260--3-T).

Best regards

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