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Multiple target sockets with multiple b_transport functions in one class?

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In SystemC, we have the possibility to bind a specific b_transport function to a specific target socket. Hence, I can create a module with multiple target sockets that each bind to their own b_transport implementation.

Reading the UVM user's guide v1.2 chapter 2.47 (TLM2 - Use Models), I get the impression that there exists an implicit binding between all target sockets of a module and one b_transport implementation. In other words, we can only have one b_transport function per uvm_component. Is that correct, or is there a way to implement and bind different b_transport implementations to different target sockets?

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By using convenience sockets, you can bind each socket to a different function (names will have to be different because the argument types are the same). Thus, twotarg.hpp:

// Example code with two target sockets and separate implementations

#ifndef TWOTARG_MODULE_HPP
#define TWOTARG_MODULE_HPP
#ifndef SC_INCLUDE_DYNAMIC_PROCESSES
#define SC_INCLUDE_DYNAMIC_PROCESSES
#endif
#include <tlm>
#include <tlm_utils/simple_target_socket.h>
#include <cstdint>

// Specific symbols for convenience
using sc_core::sc_time;
using sc_core::sc_event;

struct Twotarg_module: sc_core::sc_module
{
  // Type definitions to improve readability
  using tlm_payload_t = tlm::tlm_generic_payload;
  using tlm_phase_t   = tlm::tlm_phase;
  using tlm_peq_t     = tlm_utils::peq_with_cb_and_phase<Twotarg_module>;

  // Sockets, ports and exports
  tlm_utils::simple_target_socket<Twotarg_module> targ_socket_2{ "targ_socket_1" };
  tlm_utils::simple_target_socket<Twotarg_module> targ_socket_2{ "targ_socket_2" };

  Twotarg_module ///< Constructor
  ( sc_core::sc_module_name instance_name
  );
  ~Twotarg_module( void ); ///< Destructor (allow PIMPL)
  virtual const char* kind( void ) const override { return "Twotarg_module"; }

private:
  //----------------------------------------------------------------------------
  // Forward interface
  void b_transport_1( tlm_payload_t& trans, sc_time& offset );
  void b_transport_2( tlm_payload_t& trans, sc_time& offset );
private:
  Twotarg_module( const Twotarg_module& ) = delete;
  Twotarg_module& operator=( const Twotarg_module& ) = delete;

};

#endif /*TWOTARG_MODULE_HPP*/

and twotarg.cpp:

//File: twotarg.cpp
#include "twotarg.hpp"
namespace {
  const char* const MSGID{"/Doulos Inc./Example/Twotarg"};
}
using namespace sc_core;
using namespace tlm;
using namespace std;

//------------------------------------------------------------------------------
Twotarg_module::Twotarg_module // Constructor
( sc_module_name instance_name
)
{
  targ_socket_1.register_b_transport        ( this, &Twotarg_module::b_transport_1 );
  targ_socket_2.register_b_transport        ( this, &Twotarg_module::b_transport_2 );
}

//------------------------------------------------------------------------------
// Destructor
Twotarg_module::~Twotarg_module( void )
{
}

////////////////////////////////////////////////////////////////////////////////
// Forward interface

//------------------------------------------------------------------------------
void
Twotarg_module::b_transport_1
( tlm_payload_t& trans
, sc_time& delay
)
{
  SC_REPORT_INFO_VERB( MSGID, "Not yet implemented", SC_NONE ); ///< replace this line
  // TO BE SUPPLIED
  // Check attributes
  // Perform transaction
}

//------------------------------------------------------------------------------
void
Twotarg_module::b_transport_2
( tlm_payload_t& trans
, sc_time& delay
)
{
  SC_REPORT_INFO_VERB( MSGID, "Not yet implemented", SC_NONE ); ///< replace this line
  // TO BE SUPPLIED
  // Check attributes
  // Perform transaction
}

///////////////////////////////////////////////////////////////////////////////
// Copyright 2019 by Doulos Inc.. All rights reserved.
//END twotarg.cpp

 

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Thanks David, but I already know about the SystemC side  🙂

I'm looking for possibilities in the UVM-SV space (hence the post in "UVM SystemVerilog Discussions").

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