pvr Posted March 21, 2019 Report Share Posted March 21, 2019 Hi All, i am new to Assertions, can you any one help me on how to check the phase difference in two clocks. Thanks in Advance, PVR Quote Link to comment Share on other sites More sharing options...
Stephan Gerth Posted March 21, 2019 Report Share Posted March 21, 2019 Hi PVR, this is probably the wrong sub-forum for that question. As your title suggests you are interested in SystemVerilog Assertions but this sub-forum is more oriented to SystemC verification. You probably will get more response about SystemVerilog Assertions in other forums such as https://verificationacademy.com/forums/systemverilog. Quote Link to comment Share on other sites More sharing options...
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