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pvr

System verilog Assertions

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Hi All, 

i am new to Assertions, can you any one help me on how to check the phase difference in two clocks. 

Thanks in Advance,

PVR

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Hi PVR,

this is probably the wrong sub-forum for that question. As your title suggests you are interested in SystemVerilog Assertions but this sub-forum is more oriented to SystemC verification. You probably will get more response about SystemVerilog Assertions in other forums such as https://verificationacademy.com/forums/systemverilog.

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