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Hi All ,

I'm exploring uvmsc as a vitrifaction strategy .Does any one did already with TLM 2.0 model interface .If yes please share me the example to integrate in my environment .As per LRM 


interfaces are defined.

NOTEUVM-SystemC does not yet define the TLM-2.0 blocking and non-blocking transport interfaces, direct memory interface (DMI), nor a debug transport interface. Use the SystemC TLM-2.0 interfaces instead. 


What does use SystemC TLM2-0 mean .Please help me on these .




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Hi Charan,


uvm_(non)blocking_*_port are SystemC TLM-1.0 based UVM-SystemC ports. As stated in your referenced NOTE, UVM-SystemC has not yet defined TLM-2.0 transport interfaces etc.. Hence, in case you need SystemC TLM2.0 based interfaces, you need to use the ones provided by SystemC itself.


In case you have a SystemC model with TLM2.0 based interfaces, you have (at least) two options to verify this with a UVM-SystemC environment:

  • create a UVM driver that contains initiator/target sockets in order to connect directly to your model
  • instantiate a signal-to-TLM2 / TLM2-to-signal adapter between a signal level driver and your model


P.s. you probably meant "verification" i.s.o. "vitrifaction", but at least I learned a new word 😉  https://en.wikipedia.org/wiki/Vitrification



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I agree with Bas, recently integrated a model to UVM driver/component using standard  TLM socket (simple_initiator_socket), tried with TLM put port first but didn't work.


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