katang Posted January 25, 2019 Report Share Posted January 25, 2019 My submodules have status bits like sc_out<bool> Pooled;// If this module is in the pool in the module, I have sc_in< sc_dt::sc_uint<No_OF_SUBMODULES> > Pooled;//status bits of the modules What is the best way of connecting the individual bits to the corresponding bits of the word? (I want to activate the main module upon status change in any of the submodules) Quote Link to comment Share on other sites More sharing options...
Eyck Posted January 25, 2019 Report Share Posted January 25, 2019 There is no predefined way. You would have to have No_OF_SUBMODULES sc_signal<bool> connecting to the sc_out<bool>, one sc_signal<sc_dt::sc_uint<No_OF_SUBMODULES>> connecting to the sc_in<..>, and a SC_METHOD. The method needs to be sensitive to the bool signals, assemble the sc_uint and write it to the sc_uint signal. HTH Quote Link to comment Share on other sites More sharing options...
katang Posted January 25, 2019 Author Report Share Posted January 25, 2019 You are right, but I have a high number of modules, and it is a very ugly code to be sensitive to so many signals. If my submodules (working concurrently) are manipulating sc_uint, I have synchronization issues. Quote Link to comment Share on other sites More sharing options...
Roman Popov Posted January 25, 2019 Report Share Posted January 25, 2019 7 hours ago, katang said: You are right, but I have a high number of modules, and it is a very ugly code to be sensitive to so many signals. If my submodules (working concurrently) are manipulating sc_uint, I have synchronization issues. Can you explain what you mean by "ugly"? You don't want to create many events? Or you don't want to connect every module manually? Second problem can be solved with a loop. Quote Link to comment Share on other sites More sharing options...
katang Posted January 26, 2019 Author Report Share Posted January 26, 2019 Maybe you are right, but I have not yet seen "sensitive" in a loop. I am not used to that style, that is all. BTW: In this way the bits of a word are changed in a concurrent way. As the single bits from the submodules are connected individually to the bits of the word in the module, I guess there might not be any hazard in the electronic implementation. Also, as long as SystemC routines are executed in one thread, similarly no problem in the simulator. Am I right? In the future multithread versions of SystemC, may this change? Quote Link to comment Share on other sites More sharing options...
Roman Popov Posted January 26, 2019 Report Share Posted January 26, 2019 1 hour ago, katang said: BTW: In this way the bits of a word are changed in a concurrent way. As the single bits from the submodules are connected individually to the bits of the word in the module, I guess there might not be any hazard in the electronic implementation. Also, as long as SystemC routines are executed in one thread, similarly no problem in the simulator. Am I right? In the future multithread versions of SystemC, may this change? Check section 4.2 "Simulation" of SystemC standard. Values of signals change in "Update Phase", so they don't depend on process evaluation order. Quote Link to comment Share on other sites More sharing options...
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