Timestep consistency between two TDF modules

[sgira]

I have two TDF modules and one LSF module interconnected as shown in the figure:

Now my problem is that the controller should send the "command" and "threshold" signals much slower than the Valve send the "aperture" signal and the water tank update its water level. I tried to change the timesteps of tdf modules and the timesteps of relative ports and rates to be consistent, but when I run with different timestep the scheduler still say: 

Inconsistency in timestep assignment between
 module: system.valve     timestep: 1 s (1 Hz)           expect: 5 s (0.2 Hz)
     and  module: system.controller     T: 5 s (0.2 Hz)        or expect: 1 s (1 Hz)

     rate1/rate2= 1/1     dT: 4 s

or 

Error: SystemC-AMS: System not schedulable - no element schedulable.

or

Error: SystemC-AMS: Sample rates are inconsistent in : sca_linear_solver_0 containing modules (max. 5 printed):
		system.watertank.tdf2lsf
		system.watertank.gain1
		system.watertank.sub1
		system.watertank.gain2
		system.watertank.lsf2tdf
 at outport 0 ch_max_sample: 1 n_sample: 10

...depending by the settings in attribute methods of the TDF modules.

I want only run the TDF controller slower (e.g. 5s) than the Valve and the Water Tank (e.g. 1s). Anyone can help me please?

[maehne]

To achieve activation of your TDF controller only once per 5 activations of the valve and water tank modules, you will need to assign in addition to the time step also consistent rates to the TDF ports. E.g., you could assign to the TDF controller outputs command and threshold a rate of 5. Then, the connected valve and water tank modules will be activated 5 times per activation of the controller. As then the water tank will also output 5 times a water level sample to be read by the controller module, you will also need to assign a rate of 5 to the controller's input port. At this point, the TDF cluster is still not schedulable, as you have a feedback loop, which requires the insertion of a proper number of delay samples to achieve causality. To this end, you could, e.g., assign a delay of 5 to the controller input.

For better understanding of the basic concepts of TDF modeling, I strongly suggest that you read at least the section 2.1 "Modeling fundamentals" of the SystemC AMS User's Guide available from the Accellera website.

 

[sgira]

Thank you maehne! After I read your suggestion and after I read the TDF section of the user guide better, finally I have reached the goal! The trick is to oversample the signal in the controller output so that the valve can run faster, and then I set the same rate and delay for the controller input port so that it can consume and wait all samples produced by the other modules.

For simplicity, here is an image taken from the user guide that can help the readers of this topic:

[maehne]

Glad I could help! You have grasped the idea correctly.