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Issue with clocking block output

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Iam seeing issue with mux output from clocking block(Inputs(a,b,sel) are delayed correctly by 1ns where as outputs is in sync with clk).

DUT definition:

module mux(a,b,sel,clk,out);

input [4:0] a;

input [4:0] b;

input clk;

input sel;

output [4:0] out;

reg [4:0] out_temp;

always @(posedge clk) begin

if(sel==0) out_temp <=a;
if(sel==1) out_temp <=b;


assign out =out_temp;


Interface definition:


interface mux_if(input clk);

logic [4:0] a;

logic [4:0] b;

logic sel;

logic [4:0] out;

clocking mux_cb @(posedge clk);

   default  input #1ns output #1ns;

   input  out;

   output a,b;
   output sel ;



In TB iam instantiating DUT as 

mux mux_inst(.clk(mux_if1.clk),




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