Jump to content
Sign in to follow this  
Khushi

Changes in generic paylod are not reflected in UVM side

Recommended Posts

Hi Guys

I have a scenario where I have an target module in SystemC-TLM2 with a tlm_target_socket.

I developed a UVM based verification env to verify that SystemC-TLM2 model.  In UVM test bench I have an initiator module which calls b_transport with some payload and in SystemC-TLM2 target side I have the implementation of b_transport.

I can see the the payload reaching on systemc side but when I change the payload (e.g. data or address) in b_transport implementation, the changes are not reflected on UVM initiator after the b_transport call returns.

I am not able to understand what is going wrong. Any help or guidance will be highly appreciated,

I am using Cadence UVM-ML for this.

Thanks

Khushi

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now
Sign in to follow this  

×