Lynn Garibaldi 11 Report post Posted June 13, 2018 The Accellera UVM Working Group has released the UVM 2017 0.9 reference implementation. This implementation is available as a SystemVerilog class library and is fully compatible with the IEEE 1800.2-2017 standard as defined in the Language Reference Manual. The library can be downloaded for free here. The IEEE 1800.2-2017 standard is available free of charge from the IEEE Get program, courtesy of Accellera. We encourage you to use this forum to provide feedback, ask questions, and engage in discussions. Share this post Link to post Share on other sites
sas73 0 Report post Posted July 7 Are there any plans on continuing using the GitHub repository for such releases or has it been discontinued? Share this post Link to post Share on other sites
Roman Popov 55 Report post Posted Friday at 07:28 PM On 7/7/2019 at 12:12 AM, sas73 said: Are there any plans on continuing using the GitHub repository for such releases or has it been discontinued? This is not official Accellera repository. But in case your company is Accellera member you can request access to Accellera UVM git repositories. Share this post Link to post Share on other sites
