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ljepson74

time slot vs. time step (1800.1-2017.pdf)

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As used in the SystemVerilog LRM, 1800.1-2017.pdf, what is the difference between these two terms? 

The first seems well defined.  The second, not so much.

* time slot

* time step

 

 

 

Cliff Cummings/Sunburst Design wrote the following in CummingsSNUG2006Boston_SystemVerilog_Events.pdf:

Quote

"The IEEE Std 1800-2005 standard sometimes referred to a time slot as a timestep, but the term timestep has been removed from the P1800-2008 Draft Standard."

If that is correct, then it seems the term 'time step' has returned.

Edited by ljepson74
To change a "code insertion" to a "quote insertion".

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Both the 2005 and 2017 LRMs contain this statement:

Quote

"The step time unit is equal to the global time precision."

The 2017 LRM also states:

Quote

"The global time precision, also called the simulation time unit, is the minimum of all the timeprecision
statements, all the time precision arguments to timeunit declarations, and the smallest time precision
argument of all the `timescale compiler directives in the design."

 

So, in searching for the definition of "time step", as used in the 2017 LRM, I should have been searching for just "step".

In response to my question above, I offer the following definition of the relationship between "time slot" and "time step".

A "time step" is the distance between two adjacent "time slot"s, or is simply used to refer to a successive "time slot".   i.e. When you advance a "time step", you simply move to the next time slot.

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What is the proper forum to request that this be more clear in the next LRM release?  Should I send that request to the IEEE now, instead of Accellera?

Request: 
1) "time step" vs "step time" - Use only one or the other (or state their equivalence, to help people who search the doc for the term).
2) Describe relationship between "time step unit" and "time slot".
 

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