Jump to content
Roman Popov

Why Accellera does not offer SystemC to Verilog converter?

Recommended Posts

Verilog is currently supported by all major FPGA and ASIC synthesis vendors. This is why all other HDLs build on top of general purpose programming language offer Verilog converters. Verilog conversion is supported by Chisel (Scala), MyHDL (Python), CλaSH (Haskell).  But there is no one for SystemC. 

This I think is a serious issue for SystemC adaption as hardware design language.  Especially in academia, where students are generally using free tools for learning, like free versions of FPGA design suites.

Share this post


Link to post
Share on other sites

SystemC is very well adopted already and has no need to provide free tools. Also, the purpose of Accellera is to develop standards for the EDA and engineering community, not free tools for academia. For this it has done quite well and continues to do an excellent job. Accellera is made up of volunteers from member companies and many of these do not get paid for their participation. In fact, there are very few that are paid staff for Accellera, and most of those are administrative only without the necessary skills to develop such tools. All contributions for Accellera are strictly volunteer and donations. More to the point, member companies develop and sell tools that do exactly what you are asking. So they have zero motivation to give away what they use to create income for themselves.

So if you would like to develop such a tool on your own time and donate it, I am certain others would applaud your efforts; however, you should also not be surprized if your donation is rejected because it might hurt existing products of the member companies.

If you would like to get a full time job with one of the member companies, do not be surprised to learn they expect you to have knowledge in SystemC to do some of the work you are hired for. Some companies might even send you to get trained.

Finally, if you are interested in "free" tools that convert SystemC to Verilog, you might want to checkout Xilinx Corporation's VivadoHLS, which is as close to free as I think you will get for this type of very complex tool. It is restricted to developing code to be used inside Xilinx FPGA's and does a very decent job. You can also talk with other EDA companies about the possibility as a student of your university acquiring low cost versions of other commercial tools for use in graduate classes.

Share this post


Link to post
Share on other sites
1 hour ago, David Black said:

SystemC is very well adopted already and has no need to provide free tools. Also, the purpose of Accellera is to develop standards for the EDA and engineering community, not free tools for academia. For this it has done quite well and continues to do an excellent job. Accellera is made up of volunteers from member companies and many of these do not get paid for their participation. In fact, there are very few that are paid staff for Accellera, and most of those are administrative only without the necessary skills to develop such tools. All contributions for Accellera are strictly volunteer and donations. More to the point, member companies develop and sell tools that do exactly what you are asking. So they have zero motivation to give away what they use to create income for themselves.

Yes, I've noticed that in my company. People who contribute to SystemC are doing that in a spare time. Which is strange: software companies have full-time employees working on language standards and opensource compilers (C++ itself is an example).  

Quote

So if you would like to develop such a tool on your own time and donate it, I am certain others would applaud your efforts; however, you should also not be surprized if your donation is rejected because it might hurt existing products of the member companies.

What I was talking about is a translator for cycle-accurate RTL models, not an HLS tool. So it would not hurt any business, but rather to promote SystemC as a design language.

Quote

Finally, if you are interested in "free" tools that convert SystemC to Verilog, you might want to checkout Xilinx Corporation's VivadoHLS, which is as close to free as I think you will get for this type of very complex tool. It is restricted to developing code to be used inside Xilinx FPGA's and does a very decent job.

I did not know that Vivado HLS is included into free WebPack version.  This explains why we are seeing students running SystemC in Vivado on this forum. Will try it to compare how good it is vs SystemC synthesis from EDA companies.

Quote

You can also talk with other EDA companies about the possibility as a student of your university acquiring low cost versions of other commercial tools for use in graduate classes.

I know, universities can buy licenses EDA licenses for very low cost. When I was a student we got commercial tools installed in university. But still you can't install them on your own laptop for learning at home. So free FPGA tools were always the best for practice.

Share this post


Link to post
Share on other sites

For what it is worth, there are several open-source tools developed by academia available, which translate SystemC RTL descriptions to Verilog and vice versa: 

SC2V: https://opencores.org/project,sc2v

GSC: https://opencores.org/project,gsc

SysC2Ver: http://sysc2ver.sourceforge.net

Verilator: https://www.veripool.org/wiki/verilator

Verilog2C++: http://verilog2cpp.sourceforge.net

... and probably others, which can be found through a web search. The development of most of these projects was not very active over the past years, but as they are open-source, you're free to pick them up.

Otherwise, I fully agree with David's statement that it is not the task of Accellera to develop such tools and also not in the commercial interest of EDA tool vendors, as it is in an area, where they can differentiate themselves most from their competition. For academia and industry there might be some interest for open-source tools as a base for custom tooling, which has to fulfil very particular needs.

 

Share this post


Link to post
Share on other sites
5 hours ago, maehne said:

For what it is worth, there are several open-source tools developed by academia available, which translate SystemC RTL descriptions to Verilog and vice versa: 

SC2V: https://opencores.org/project,sc2v

GSC: https://opencores.org/project,gsc

SysC2Ver: http://sysc2ver.sourceforge.net

Just for the record: None of them works, nor actively maintained.

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now

×