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2 hours ago, David Black said:

SystemC is not suited well to RTL.

This is not true. We use SystemC for RTL when we need to create highly-configurable RTL IPs.

Also SystemC RTL has advantage in code sharing with VPs. So for example if I write UART in SystemC I can reuse CSR code between RTL and VP.

And SystemC is better for FSMs, because CTHREADs are synthesizable. Unlike Verilog/VHDL where you need to code FSM state explicitly. (This is of course Verilog/VHDL synthesis tools limitation, not languages limitation ) 

The only major drawback of SystemC is specifying combinatorial circuits, because SystemC has no wildcard sensitivity lists, like always @* in Verilog.

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