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rsmitra09

one full example

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Given that this concept of a high level test specification is fairly new, what is critically needed is one complete example which shows the entire flow of usage. The videos from DAC-2017 show some code snippets from an UART/DMAC example, but that also does not show the complete code.

So I have taken the code snippets from the DAC tutorial, and put them together as one full code (see below). Can this example be corrected, more details added (for instance, variations for inferring from incomplete specifications) and the full code be added to the next version of the manual?

While creating this example, I noticed one problem in the grammar.  In the instantiation of action rd_i in pss_top, where will the action read_in_a be found? The grammar allows only one identifier as the type, so the following hierarchy of names is not allowed today:

action data_rx_a {
    uart0.read_in_a rd_i; // "uart0." prefix added
}

The full code (as I have understood it) is given below:

// uart example, copied from dac2017-part1 video
// approximate time of occurance - mentioned as comments
// some extra lines added, for missing symbols

// at 30:31 ======================================
stream data_stream_s {
    rand int size;
    int addr; //added
}
buffer data_buff_b {
    rand int size;
    int addr; //added
}
// at: 42:50 ==========================================
resource dma_channel_r {
    bit[5:0] instance_id; // added
}
struct dma_xfer_params_s {
    rand bit[1:0] mode;
    rand bit[31:0] src_addr;
    rand bit[31:0] dst_addr;
    rand bit[5:0] chan;
}
// at: 44:20 ===================================
component uart_c {
    //import dma_xfer_pkg::*; // not needed, using above code
    resource uart_r {};
    pool [1] uart_r uart_p;
    bind uart_p {*};
    action read_in_a {
        output data_stream_s data;
        lock uart_r myuart;
        constraint c1 {data.size % 4 == 0;}
    };
}
// at: 45:20 ===================================
component dmac_c {
    pool dma_channel_r chan_p;
    bind chan_p {*};
    action q2m_xfer_a { // details added from 42:50
        input data_stream_s in;
        output data_buff_b out;
        lock dma_channel_r chan;
        rand dma_xfer_params_s params; //rand duplicated here?
        constraint c1 {in.size == out.size; }
        constraint params_c {
            params.mode == 'b01;
            params.src_addr == in.addr;
            params.dst_addr == out.addr;
            params.chan == chan.instance_id;
        }
    }
}
// at: 47:06 ===================================
component pss_top {
    uart_c uart0;
    dmac_c dma0;
    pool data_stream_s stream_p;
    bind stream_p {*};
    pool data_buff_b buff_p;
    bind buff_p {*};
    action data_rx_a { // at 32:29 ===============
        read_in_a rd_i; // need to add "uart0." prefix
        q2m_xfer_a q2m; // need to add "uart0." prefix
        constraint c1 {q2m.in.size % 4 == 0;}
        bind rd_i.data q2m.in;
        activity {
            parallel {
                rd_i;
                q2m;
            }
        }
    }
}

 

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