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Parameterizable enum missing

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SystemVerilog had a cool features where it was possible to specify a sequence of enum literals:

typedef enum {
} some_enum;

This would generate an enum with the literals SOME_LITERAL0, SOME_LITERAL1, ..., SOME_LITERAL9.

This was pretty useful in building generic code that can deal with a configurable number of states, transfers, whatever. I noticed this feature is missing in the PSS. This could easily be supported in the DSL, but it's probably more difficult (if at all possible) to implement in C++. Is this the reason it's not in there? There are other sections in the document that specifically state that some feature is not available in the DSL/C++ version, so adding it do the DSL and not to C++ would be consistent.

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From PSWG:

Support for generated enumearage (e.g. 'typedef enum {sub[5]} myEnum;' that results in 5 enums sub0 thru sub4 with values 0 thru 4 respectively) could be added.  This functionality does not seem to be key to PSS but more of a  convenience.  Do not propose adding this functionality at present.

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