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UVM Override V/s Simulator Compile/Elab

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Hi Folks, 

Interestingly today making some tweaks I faced a scenario with overrides.

Suppose I add some variables in the extended class which are not present in the base class.

Then I called the uvm_set_type_override from my top test.

Interestingly I wanted to access those newly added variables in final_phase of some component , but during the simulator compile/elaboration phase it fails since the overrides are active during Simulation run-UVM_BUILD_PHASE.

So my question is , if someone using some legacy code and wanted to update the stuff without re-writing again/or major changes , extended from base, then only overrides possible are those that will be active during simulation run , for an example , setting default sequence to driver with override.

So there is no way we could leverage it.

I am wandering , if TLM-GP extensions implementation may provide my some idea to do this.

Any suggestions ???

If needed a code to see  I saved the stuff http://www.edaplayground.com/x/2Ltr

Line 156 is point of interest




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