UVM Override V/s Simulator Compile/Elab

[karandeep963 8]

Hi Folks, 

Interestingly today making some tweaks I faced a scenario with overrides.

Suppose I add some variables in the extended class which are not present in the base class.

Then I called the uvm_set_type_override from my top test.

Interestingly I wanted to access those newly added variables in final_phase of some component , but during the simulator compile/elaboration phase it fails since the overrides are active during Simulation run-UVM_BUILD_PHASE.

So my question is , if someone using some legacy code and wanted to update the stuff without re-writing again/or major changes , extended from base, then only overrides possible are those that will be active during simulation run , for an example , setting default sequence to driver with override.

So there is no way we could leverage it.

I am wandering , if TLM-GP extensions implementation may provide my some idea to do this.

Any suggestions ???

If needed a code to see  I saved the stuff http://www.edaplayground.com/x/2Ltr

Line 156 is point of interest

 

 

 

[kirloy369 0]

You cannot reference to "abc" on handle of my_transaction type. Try using $cast as below.

begin
  extended_transaction  etx;
  if($cast(etx,tx))
    $display("DEBUG_CODE: IN driver abc = %d",etx.abc);
end

 

[karandeep963 8]

Yes it should work. It skipped from my mind.

Thanks a lot :)