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uvm_sequence_item
Creating the right sequence item structure in UVM

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Hi All,

I have a typical use case, where the sequence item w.r.t driver is always the same, but it's view needs to change while writing constraints.

The fields of sequence items to write constraints change w.r.t the header type, there are around 25-30 types of headers. 

What is the best way to create the base sequence item in this case in line with UVM methodology?

Example:-

bit [32] header; //Actual header as seen by driver

The format of the header is however dynamic:-

format-1 :

bit[31:21] header_type;

bit[20:10] field_2_type_1;

bit[9:0] field_3_type_1;

format-2:

bit[31:21] header_type;

bit[20:15] field_2_type_2;

bit[14:8] field_3_type_2;

bit[7:0] field_4_type_2;

format-3:

bit[31:21] header_type;

bit[20:12] field_2_type_3;

bit[11:6] field_3_type_3;

bit[5:0] field_4_type_3;

.......

......

I currently have though of a packed union of different structures to be one of the solutions for this type of scenario. This union will be a member of the sequence_item class and the structure will be representation of the different formats of header.

Is there a better means of creating polymorphic sequence items in UVM.

I am ok to try some system verilog hacks in uvm too for a solution.

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