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Roman Popov

How to model a delay line in SystemC

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Hi all,

I'm pretty ignorant in SystemC and I've started to learn it so be kind. What is the point to use a delay assignment in a SC_METHOD ? If you are using an SC_METHOD, I guess you are interested to synthesize the module.The delay assignments are basically ignored by the synthesizer and in some cases they can lead to some problems in a soc level verification.

The only use I can think about in VHDL of the delay is to fix the delta delay problem but I'm not sure if the SystemC is affected to this problem.

 

Cheers,

Stefano

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1 hour ago, campo85 said:

What is the point to use a delay assignment in a SC_METHOD ? If you are using an SC_METHOD, I guess you are interested to synthesize the module.

I've needed it for test environment modeling purposes, not for synthesis.

 

Quote

The only use I can think about in VHDL of the delay is to fix the delta delay problem but I'm not sure if the SystemC is affected to this problem.

Delta delay problems (also known as Shoot-thru) are possible in synthesizable SystemC. Common case is when you have a clock gate that inserts a delta delay into a clock signal distribution network. 

However in SystemC it is solved in a different way: Instead of delaying all assignments, you use immediate notifications inside clock signal, so that processes sensitive to gated clock are executed in the same delta cycle with processes sensitive to ungated clock.

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