Jorge

Tri-State buffer modeling

2 posts in this topic

Hi there, I'm an engineering student from Venezuela and working on systemC for a class project.

I'm having a bad time trying to make a tri-state buffer model on system C.

I know there is sc_logic and sc_lv but I just don't know how to work with this two data types.

I'm working a project (a microprocessor) and I need to model a tri-state module to hook up with my registers so I'll be able to have control on the data coming out of the registers.

In case you wonder here is more info https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Build/implRegFile.html

Any idea on how to model a tri-state buffer module?.

thanks in advance.

Share this post


Link to post
Share on other sites

For that kind of modelling you probably need resolved types, e.g. sc_signal_resolved, sc_in/out resolved. These types model signal strength resolution, i.e. if you drive two values such as '1' and 'Z', '1' will be the resulting value because '1' is stronger than 'Z'.

Have a look at the SystemC standard 1666-2011, especially section 6.13.5 where there's a little example that might help,

 

regards

Alan

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!


Register a new account

Sign in

Already have an account? Sign in here.


Sign In Now