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SystemC - Splitting the output sampling

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Hi,

I'm novice to SystemC and CtoS.

I'm evaluating the possibility to replace our existing methodology (Verilog) with SystemC and HLS.

Unfortunately, the results are terrible for now (we have designs which are already in production and we can compare the netlists) and for us power and area are huge issue.

I haven't given up yet, but it appears that simply using the algorithm model (C++) and playing with the CtoS won't be sufficient. So I've decided to rewrite the code itself.

One of the most common scenarios that I've observed in the generated RTL is the issue presented in the attached test-case:

Assuming we have a very long counter, we would like to gate the MSB bits and update only the LSB bits. When the LSBs are wrapping up I'll enable the MSBs for a single clock cycle. Now when producing the attached code, I get a single 8-bit register, but it is constantly updated. When adding an internal variable to control the sampling, I get 2 additional registers of 4 bit each, but the 8-bit register is left in place.

So basically the question is how I fix the code, without splitting the ports, so that I get 2 4-bit registers toggling only when needed?

post-17810-0-73783300-1474650609_thumb.png

post-17810-0-44989600-1474650621.png

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Hi, your approach seems odd to me. If I were you, I would re-write the C++ model to be more synthesisable. I would go back to your HLS vendor and say "what do I need to do to my algorithmic model to get good results?

 

You seem to be taking the approach of using HLS, then re-writing the generated RTL code, which sounds like a very long-winded design flow,

 

regards

Alan

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