tjroamer Posted August 2, 2016 Report Share Posted August 2, 2016 Hi, I am just curious whether it is possible to represent both TLM and RTL variant in one single IP-XACT file. For a component, we have only one model node, which contains serveral ports. The component can also have bus interfaces sitting at a higher level. For a specific model port, I have two variants, let's say: VHDL: p_int: std_logic SystemC:p_INT: sc_in<bool> Note that they have different names. I need to specify a specific name in the port node. The current solution is that I generate two IP-XACT files, one for RTL and the other for TLM, both have their specific different name in the file. I checked out the Leon2 example, where I found two different component IP-XACT file sets Leon2RTL and Leon2TLM, where for instance the component dma has been defined twice. My question is: is this an intended use case for the IP-XACT to apply one single IP-XACT file to represent two variants with different languages? Thanks. Quote Link to comment Share on other sites More sharing options...
kock Posted August 2, 2016 Report Share Posted August 2, 2016 Hi Kenny, Yes, IEEE 1685-2014 supports RTL and TLM views in a single file. Please read this topic http://forums.accellera.org/topic/5070-views-in-a-componentmodel/ were the question was asked before. Best regards, Erwin Quote Link to comment Share on other sites More sharing options...
tjroamer Posted August 2, 2016 Author Report Share Posted August 2, 2016 Hi Kenny, Yes, IEEE 1685-2014 supports RTL and TLM views in a single file. Please read this topic http://forums.accellera.org/topic/5070-views-in-a-componentmodel/ were the question was asked before. Best regards, Erwin Hi Erwin, thanks for your answer. I overlooked that topic. Now it is clear to me, in my case, I have to define two ports in the model->ports element, and then assign TLM view to p_INT and RTL view to p_int with language specific data type using wireTypeDefs Best regards, /Kenny Quote Link to comment Share on other sites More sharing options...
tudor.timi Posted August 18, 2016 Report Share Posted August 18, 2016 I'm being overly pedantic here, but p_INT: sc_in<bool> doesn't really seem all that TLM to me. TLM would be stuff like sockets and ports. You seem to have two RTL-ish views, one in VHDL and one in SystemC. Quote Link to comment Share on other sites More sharing options...
tjroamer Posted August 20, 2016 Author Report Share Posted August 20, 2016 I'm being overly pedantic here, but p_INT: sc_in<bool> doesn't really seem all that TLM to me. TLM would be stuff like sockets and ports. You seem to have two RTL-ish views, one in VHDL and one in SystemC. This is correct. The p_INT is not TLM style, but since I have to generate a systemc model, which contains both signal and transactional level ports in one component. These ports need to be assigned to a view for the design configuration. In this case, I assigned all of the systemc-relevant ports and sockets to TLM view. Not very accurate, but I don't see any better solutions so far. Quote Link to comment Share on other sites More sharing options...
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