priority for uvm_reg transactions

[proo]

There are many threads/virtual sequences in the test that will initiate register transactions through a shared register model/bus agent. I want to give specific sequences higher priority so they will complete more quickly even when the bus is fully utilized.

 

I tried set_arbitration(SEQ_ARB_STRICT_FIFO) on the bus sequencer, but now see this fatal message from it on the first transaction:

[sEQDEFPRI] Sequence default_parent_seq has illegal priority: -1

 

I thought that if priority is not specified, it should default to a value like 100 and thus behave the same way as SEQ_ARB_FIFO (the default). Is there something wrong with the env setup?

 

I was planning to only set priority (to a value >100) in the virtual sequence I wanted a raised priority on, but I haven't gotten to that point yet, so feel free to comment if that will work as well.

 

Thanks in advance!