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MikeStrom

Hierarchical vcd dumps

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Hi,

 

I'm new to SystemC, but have worked with Verilator/C++ for quite a while. We are now moving to Verilator/SystemC and have problems creating hierarchical vcd dumps from SystemC native vcd generation. The only hint i got from the documentation is to use dots to separate hierarchical levels, but it does not create a hierarchy in the vcd files.

 

I attached two screen dumps from gtkwave. The first one is a vcd generated from Verilator, the second is a vcd generated from SystemC.

 

Any suggestions are most welcome.

 

Regards,

Mike

post-16473-0-44093600-1449072789_thumb.png

post-16473-0-11018800-1449072798_thumb.png

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Hi Mike,

The dot notation should work, I would suggest you have a look at your vcd file to see if the hierarchy is recorded, you should see something like:

sc_trace(fp,top.u1.signalx,"signalx");    

$scope module top $end
    $scope module u1 $end
        $var wire 1 ^ signalx $end
    $upscope $end
$upscope $end

good luck,

Hans.

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Hi Mike,

The dot notation should work, I would suggest you have a look at your vcd file to see if the hierarchy is recorded, you should see something like:

sc_trace(fp,top.u1.signalx,"signalx");    

$scope module top $end

    $scope module u1 $end

        $var wire 1 ^ signalx $end

    $upscope $end

$upscope $end

good luck,

Hans.

 

Thanks Hans,

 

I noticed that no hierarchy is created by SystemC in the vcd files. However, i found this utility that adds proper hierarchy to the vcd. It works, except that some incompatibility prevents optimization of the vcd by gtkwave.

 

Am i having this problem because I'm doing something wrong?

 

Chers,

Mike

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