Jump to content
Sign in to follow this  

Recommended Posts



I'm newbie to SystemC TLM, coming from SystemVerilog UVM world. I would like to model our RTL in SystemC using TLM2.0 to speed up our Software Development process.


Our RTL is not memory mapped bus architecture and we would like to use custom transaction class instead of generic payload.


Is it possible to do that using TLM2.0? If yes, could you please provide me with an example. Also, I have four TLM ports communicating with each other in the same model. How does one b_transport method works with all four ports?


Is it a good idea to make a model in SystemC rather than having it in SV UVM?





Share this post

Link to post
Share on other sites

Hi Zubin,


Yes it is possible. The TLM payload extension gives programmer the ability to develop custom payload/transaction.


For b_transport method, you must provide the target with the callback function that later on you have to register it with sockets (more convenient to use). Within the same model you can register as many sockets as you want to a single callback function. You can register each of the sockets to that one callback function to provide same functionality for all of your sockets. Socket here is more like port+interface, for more accurate explanation you can refer to IEEE SystemC language reference documentation.


Since you mentioned that you want to speed up software development procests, I think SystemC - TLM is your best way to achieve it. It provides you with several abstraction level that really targets the pain in your D/V flow. For software development purpose, you could try to build the model in SystemC with TLM-LT.


I hope this helps.



Share this post

Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now
Sign in to follow this