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uvm_reg_bit_bash_seq usage..


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It looks like rg should be set to point to the register on which you want to run the uvm_reg_single_bit_bash_seq. Look at how uvm_reg_bit_bash_seq sets it on line 269 of uvm_reg_bit_bash_seq.sv (UVM 1.1).

Is this really what you want to do? The intended usage seems to be to run uvm_reg_bit_bash_seq on a whole register block, and let it run uvm_reg_single_bit_bash_seq on each register.

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It looks like rg should be set to point to the register on which you want to run the uvm_reg_single_bit_bash_seq. Look at how uvm_reg_bit_bash_seq sets it on line 269 of uvm_reg_bit_bash_seq.sv (UVM 1.1).

Is this really what you want to do? The intended usage seems to be to run uvm_reg_bit_bash_seq on a whole register block, and let it run uvm_reg_single_bit_bash_seq on each register.

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Thanks Jeff!! i was able to use both uvm_reg_single_bit_bash and uvm_reg_bit_bash_seq after some debug!!

i have two more ques regarding the uvm_reg_bit_bash_seq and registermodel.

1.i see that the reset value driven by uvm_reg_bit_bash_seq has the first bit of the register inverted ..is this normal?

2.can i view the registers in register model in the waveform window?( using cadence -ncsim 10.2)

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1. uvm_reg_bit_bash_seq walks through each bit of the register. It inverts the bit, writes the register, reads and compares, then inverts it again, writes the register, and reads and compares. So, yes, the first time the register is written, the first bit will be inverted relative to the reset value. When the sequence is all done, the register should be left in its original state.

2. uvm_reg_bit_bash_seq uses front door access, so as long as you have the register model connected to your DUT through an interface that consumes simulation time, you should be able to observe the registers changing values. The register model values will be buried in your test bench class hierarchy. It might be easier and more meaningful to observe the registers changing in your DUT.

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1. uvm_reg_bit_bash_seq walks through each bit of the register. It inverts the bit, writes the register, reads and compares, then inverts it again, writes the register, and reads and compares. So, yes, the first time the register is written, the first bit will be inverted relative to the reset value. When the sequence is all done, the register should be left in its original state.

2. uvm_reg_bit_bash_seq uses front door access, so as long as you have the register model connected to your DUT through an interface that consumes simulation time, you should be able to observe the registers changing values. The register model values will be buried in your test bench class hierarchy. It might be easier and more meaningful to observe the registers changing in your DUT.

Thanks jeff!! i can the see that the registers are changing in my DUT ..But i need to need to read the registers and see if the register model is updated any suggestions on how to check my register model for correctness.

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  • 3 weeks later...

How do you disable a particular register or field in a register from being bit bashed?

I tried this example but it doesn't work:

uvm_reg_bit_bash_seq reg_bitbash ;

reg_bitbash = reg_bit_bash_seq::type_id::create("reg_bitbash", this);

reg_bitbash.model = m_env.model.eq;//set the register model for the seq

//I'm trying to disabe MY_REGISTER below with "NO_REG_BIT_BASH_TEST", but though it compiles and simulates, it doesn't remove MY_REGISTER from the bit bash.

uvm_resource_db#(bit)::set({"*", m_env.model.eq.MY_REGISTER.get_full_name(),".*"}, "NO_REG_BIT_BASH_TEST",1,this);

reg_bitbash.model.reset();

reg_bitbash.start(m_env.crb_m_agent.m_sequencer);

reg_bitbash.model = m_env.model.eq;//set the register model for the seq

//doesn't work below, though it compiles and simulates

uvm_resource_db#(bit)::set({"*", m_env.model.eq.MY_REGISTER.get_full_name(),".*"}, "NO_REG_BIT_BASH_TEST",1,this);

reg_bitbash.model.reset();

reg_bitbash.start(m_env.crb_m_agent.m_sequencer);

After this, the simulation runs and does the bitbashing of all the registers, and includes the register

that I don't want to be bitbashed.

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  • 11 years later...
On 9/3/2011 at 8:07 AM, caprice24 said:

How do you disable a particular register or field in a register from being bit bashed?

I tried this example but it doesn't work:

uvm_reg_bit_bash_seq reg_bitbash ;

reg_bitbash = reg_bit_bash_seq::type_id::create("reg_bitbash", this);

reg_bitbash.model = m_env.model.eq;//set the register model for the seq

//I'm trying to disabe MY_REGISTER below with "NO_REG_BIT_BASH_TEST", but though it compiles and simulates, it doesn't remove MY_REGISTER from the bit bash.

uvm_resource_db#(bit)::set({"*", m_env.model.eq.MY_REGISTER.get_full_name(),".*"}, "NO_REG_BIT_BASH_TEST",1,this);

reg_bitbash.model.reset();

reg_bitbash.start(m_env.crb_m_agent.m_sequencer);

reg_bitbash.model = m_env.model.eq;//set the register model for the seq

//doesn't work below, though it compiles and simulates

uvm_resource_db#(bit)::set({"*", m_env.model.eq.MY_REGISTER.get_full_name(),".*"}, "NO_REG_BIT_BASH_TEST",1,this);

reg_bitbash.model.reset();

reg_bitbash.start(m_env.crb_m_agent.m_sequencer);

After this, the simulation runs and does the bitbashing of all the registers, and includes the register

that I don't want to be bitbashed.

reg_bitbash = reg_bit_bash_seq::type_id::create("reg_bitbash", this); -> Is this correct ?? What is reg_bit_bash_seq

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