UVM Reg backdoor Read vs. Peek

[sreekrish]

UVM CRL says that a backdoor read is supposed to mimic the effect of reading a register through a physical access. I tried out an example with a WRC register and noticed that the bits are cleared only when a frontdoor read is performed. A backdoor read just returns the value of the register.

I modified a few files in the example/simple/registers/sequence_api directory to test this behavior. I have attached those files here. The register is named WRITE_CLEAR_ON_READ_REG in blk_dut module.

Edited June 9, 2011 by sreekrish

[svarun]

Hi Sreekrish,

A BACKDOOR read/write indeed mimics a FRONTDOOR read/write. But only up to updating the RTL register in case of a write and returning the status in case of a read. The access rule for a register is something that is limited to the RTL implementation and is understood when the register is accessed via the protocol interface (or FRONTDOOR). When we talk BACKDOOR we are actually bypassing this protocol interface and writing to the target register using XMR’s (direct XMR’s or VPI based). And so the BACKDOOR route is completely oblivious to the access rule and hence in this case a BACKDOOR read fails to clear the RTL register.

If you are not already aware RAL maintains a reference model of the register which is also called a “mirror”. Every register write/read() is followed up with updating the mirror. RAL also applies the access rule to the register mirror while updating it. See below.

Code illustration:

//---------------------------------------------------------------------------------------------------------

uvm_reg_data_t get_data;

model.WR_CLEAR_ON_READ_REG.read(status, rd_data, .path(UVM_BACKDOOR), .parent(this));

$display("#### WR_CLEAR_ON_READ_REG.read(BACKDOOR) yielded %0h ####", rd_data);

get_data = model.WR_CLEAR_ON_READ_REG.get();

$display("#### WR_CLEAR_ON_READ_REG.get() yielded %0h, expecting 0 ####", get_data);

model.WR_CLEAR_ON_READ_REG.read(status, rd_data, .path(UVM_FRONTDOOR), .parent(this));

$display("#### WR_CLEAR_ON_READ_REG.read(FRONTDOOR) yielded %0h ####", rd_data);

get_data = model.WR_CLEAR_ON_READ_REG.get();

$display("#### WR_CLEAR_ON_READ_REG.get() yielded %0h, expecting 0 ####", get_data);

//----------------------------------------------------------------------------------------------------------

P.S: uvm_reg::set()/get() methods are used set/query the value of the register mirror at anytime.

Results:

//-----------------------------------------------------------------------------------

#### WR_CLEAR_ON_READ_REG.read(BACKDOOR) yielded 17 ####

#### WR_CLEAR_ON_READ_REG.get() yielded 17, expecting 0 ####

#### WR_CLEAR_ON_READ_REG.read(BACKDOOR) yielded 17 ####

#### WR_CLEAR_ON_READ_REG.get() yielded 0, expecting 0 ####

//------------------------------------------------------------------------------------

There is an issue with the BACDOOR read currently as seen by the second display, the get() still yields the old value (in the case of BACKDOOR) when it should ideally have yield a 0. This is being tracked via mantis 3631 and will be fixed in the future revisions of UVM.

I hope this helped.

Thanks,

Varun