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What's the meaning of this 'process' in uvm_root.svh?

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process is a class and is part of the SystemVerilog language, not UVM/OVM, therefore you need to refer to the SV LRM for a definition.

For example, IEEE-1800-2007 section 11.9 Fine-Grain Process Control

A process is a built-in class that allows one process to access and control another process once it has started. Users can declare variables of type process and safely pass them through tasks or incorporate them into other objects. The prototype for the process class is as follows:

class process;
  static function process self();
  function state status();
  function void kill();
  task await();
  function void suspend();
  task resume();

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The process class is part of the SystemVerilog language. You're unlikely to find source code for the implementation. It's probably vendor-specific anyway. The SV LRM should provide enough description of the methods of the process class for you to use it.

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you cant give an SV implementation of that class as SV doesnt give you access to the information+functionality needed. also this is only an prototype showing the api its not something you may "extend" or use otherwise.


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