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how to create virtual sequencer

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Hi,

I have derive the virtual sequencer class from the uvm_sequencer class

class uart_tb_vsd extends uvm_sequencer;

but it reported syntax error as:

*E,SVNOTY (/home/gendaili/projects/uvm_tb/verif/sv/uart_tb_vsd.sv,4|38): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.

------

In SystemVerilog syntax, if a datatype begins with an identifier,

the identifier must refer to a type. Make sure that the typedef of the desired type

is visible in that scope or that there are not multiple wild card import clauses

importing typedefs of the same identifier name. The latter would make the use of

a simple type name ambiguous; in that case, in order to disambiguate which type is

desired you must provide a full type name of the form package_name::type_name.

What's wrong with it? is it require a specific sequence item like:

class uart_tb_vsd extends uvm_sequencer #(uart_transfer) ;

Please help me out, thanks.

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hi,

there are two causes i know for this:

1. you really need to make the declaration of the datatype visible. potentially you forgot to include the definition or you didnt import the package. please cross cehck that the datatype is really visible in that scope.

2. i see you are running with IUS. there is a known issue in recent versions of IUS which lead to an incorrect E,SVNOTY error.

regards

/uwe

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Thanks, uwes.

I have no protected or private variable since it just a test testbench.

I have deleted virtual sequencer, to make the compile pass first, maybe I can try it in VCS as well later.

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hi,

i didnt mean "local" or "protected" visibility. in sv you cant change the visibility of types with local/protected (only the visibility of instances). what i meant that very often users make simple mistakes such as a mistyped type name, a missing import statement importing the type, missing to compile the type, missing to include the file or similar.

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