Jump to content
Sign in to follow this  

Use of Vera in a UVM environment?

Recommended Posts

VCS has supported SV calling Vera and Vera calling SV for a long time. Likewise, Vera classes can be instantiated in SV, and even extended from one language to another.The two languages are close enough that one compiler can handle both languages. So keep your tried and true Vera code and use it in your UVM testbench.

Of course you need to plan how to merge the test phases in your Vera models with UVM, but the new methodology has constructs specifically designed for this.

Chris Spear


Share this post

Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now
Sign in to follow this