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Hello All,

 

I am new to AMS modeling & I have been going through some study material related to Verilog-A/Verilog-AMS.

 

I have a few questions related to AMS. I hope members here will comment.

 

1) Is AMS always needed when there is a mix of digital & analog modules in a design. For example, can it not be used for pure Analog modeling when I would like to have abstract analog models?

 

2) In most of the references, AMS is mentioned as an approach to model design blocks. In my view, AMS has to be used for creating testbench for such blocks. For example, if my design has analog interface then I have to use AMS to apply stimuli to that interface or use AMS to process output from that interface.

 

Thanks,

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This forum is related to SystemC-AMS, not Verilog-AMS. SystemC-AMS is used to model complex heterogeneous systems at an abstract level. Verilog-AMS is often used to model AMS blocks and circuits at the implementation level.

 

To answer your general questions

 

1) No. AMS modeling can be used to describe analog and/or digital behaviour, it is just a matter of abstraction. AMS modeling languages support different levels of abstraction. Low abstraction level relates to conservative behaviour, by solving Kirchhoff's voltage and current laws. Signal flow modeling approaches is an abstraction towards a non-conservative description, single quantity (voltage or current, not both) but still continuous in time. Further abstraction can be realized to data flow modeling approaches (discrete-time) or alternatively discrete-event modeling, or even transaction level.

SystemC-AMS allows you to model at different levels of abstraction, depending on the analog functionality or behaviour you would like to capture.

This is not only for analog subsystems, but also for digital subsystems. For example SystemC-AMS is very efficient to model Digital Signal Processing functions like FIR filters or IQ modulators/demodulators.

 

2) For sure, AMS modeling can be used to create AMS testbenches. Also here, it is just a matter of selecting the right abstraction level for the blocks in your testbench (stimuli, checkers, etc). Special care is always necessary at the boundary between 2 abstraction levels. This means there is not always the need to connect an analog stimuli to an analog input of the DUT, but you need to take care of the semantic difference and conversion if you cross such abstraction boundary. Often you need converter ports, modules or other interface elements in between to make the conversion from one domain (abstraction) to the other.

This is not only relevant for the interface between testbench and DUT, but also on-chip from analog subsystem A to digital subsystem B, where the abstraction level is thus different.

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Hello All,

 

I am new to AMS modeling & I have been going through some study material related to Verilog-A/Verilog-AMS.

 

I have a few questions related to AMS. I hope members here will comment.

 

1) Is AMS always needed when there is a mix of digital & analog modules in a design. For example, can it not be used for pure Analog modeling when I would like to have abstract analog models?

 

2) In most of the references, AMS is mentioned as an approach to model design blocks. In my view, AMS has to be used for creating testbench for such blocks. For example, if my design has analog interface then I have to use AMS to apply stimuli to that interface or use AMS to process output from that interface.

 

Thanks,

Hello,

What is the physical charge pump design that you are modelling ?

A very simple one would consist of a very simple CMOS inverrer

with a capacitor load. When the PMOS condutts, the capacitor

chrages and so a steady voltage value is applied to the VCO,

and when the NMOS conducts, the capacitor discharges.  Hope

that helps.

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Can you give some more background on the HLS you are aiming for? Is this HLS for digital or analog functions?

 

For analog HLS (often called analog sizing), I suggest you to contact Laboratoire d’Informatique de Paris 6 (LIP6) at Université Pierre et Marie Curie (UPMC) in Paris, France. More info:

http://www-soc.lip6.fr/en/

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