Jump to content
gaurav_brcm

X's in mirrored value (UVM hardware reset sequence)

Recommended Posts

Hi All,

I am facing an issue:

One of the register field is configured as :

 
field_a.configure(this, 12, 17, "RO", 0, 12'h0, 1, 0, 1);
field_a.set_compare(UVM_NO_CHECK);
 
While doing a reset test, first I reset model then start test.
 
But test fails with :

UVM_ERROR -- value read from DUT (0x0000000080001e00) does not match mirrored value (0x00000000XxxXfe00)

 

Basically the fields declared as RO and UVM_NO_CHECK goes X ?

 

 

Any idea what I am missing or doing wrong ?

 

Thanks.

Share this post


Link to post
Share on other sites

They don't go to X. That's just to show you that the positions where you put UVM_NO_CHECK (regardless of what access policy they have) are treated as "don't care". Your problem there is that there are some checked bits that don't match. I see an 8 and a 1e in the value read from the DUT, but I see a 0 and an fe in the mirrored value.

Share this post


Link to post
Share on other sites

No I have fields defined between 28 to 31 and thats what amazes me. These are defined as :

 

field_b.configure(this,  1, 31, "RW", 0,  1'h1, 1, 1, 1)
field_c.configure(this,  2, 29, "RW", 0,  2'h0, 1, 1, 1)
 
So X should not in bit 29 , 30  , 31.

Share this post


Link to post
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.


×
×
  • Create New...