ljepson74

SystemVerilog/UVM linting - what tools exist ?

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What tools exist for SystemVerilog/UVM linting?

 

I recently evaluated AMIQ's Verissimo (which I liked).  However, I'd like to know what else is out there.

 

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If you're a Cadence user you get HAL (HDL Advanced Linter I guess it's called, but don't let the name fool you, it can do HVLs too) included with Incisive.

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I know I am late to respond here, but we have a new start-up named VerifWorks (http://www.verifworks.com) that targets similar thing. We do have a SV, SVA & UVM linter built on top of a Python API provided by Invionics (http://www.invonics.com), however we also have a native DVRules product that is in early Beta now that works via reflection API natively with simulator of your choice. Strictly speaking DVRules (native) is "rule checker" than a linter (as in parsing level). More details soon @ our Web site.

 

Please do contact me offline if interested.

 

Warm Regards

Srini

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