Jump to content
Sign in to follow this  
pRoSpEr

Assertion system tasks error while using VCS compiler

Recommended Posts

Please consult Synopsys documentation or call your Synopsys support person for help on this. This forum is for UVM support and issues related to how UVM may differ on various simulators.

 

To my knowledge $assertvacuousoff is not part of the Proof-of-Concept simulator nor is it directly related to UVM. UVM does not address issues associated with SystemVerilog Assertions (SVA). You might want to try $assertcontrol, since $assertvacuousoff is simply a convenience task. Again, consult the vendor's documentation. In general, simulation vendors do not have uniform nor complete support for all the features of IEEE 1800-2012 yet.

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now
Sign in to follow this  

×