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kieunguyen

syntax error in VCS

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Please help me show what is syntax error in here. The text file can't be used in VCS ?

 

The input data is from text file which contains the binary values. In Modelsim, it work without error but it got problem in VCS. 

'readmemb' command is used to read binary values in text file. Some value in text file are:

1000000000011010
0000000000011010
1000000000011010
1000000000011010
1000000000011010
0000000000011010

 

I do the function simulation in VCS, and try to perform these values in some ways then run simulation but result shows following:

 

1.  Parsing design file './01cfo_im.txt'

 
Warning-[DCTL] Decimal constant too large
./01cfo_im.txt, 1
  Decimal constant is too large to be handled in compilation.
  Absolute value 1000000000011010 should be smaller than 2147483648.
 
 
Error-[sE] Syntax error
  Following verilog source has syntax error :
  "./01cfo_im.txt", 2: token is ''
  0000000000011010
 
1 warning
1 error

 

2.Parsing design file './01cfo_im.txt'

 
Error-[sE] Syntax error
  Following verilog source has syntax error :
  "./01cfo_im.txt", 1: token is '1000000000011010'
  16 'b1000000000011010
                       ^
 
3. Parsing design file './01cfo_im.txt'
 
Error-[sE] Syntax error
  Following verilog source has syntax error :
  "./01cfo_im.txt", 1: token is '1000000000011010'
  16'b1000000000011010
                      ^
 

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Alan is right. You are trying to compile the text file. This example works great for VCS with your given input: 

module tb;
  logic [15:0] mem [0:5];
  initial begin
    $readmemb("mem.dat", mem);
    foreach(mem[i])
      $display("mem[%0d]= b%b = d%d", i, mem[i], mem[i]);
  end
endmodule
vlogan +v2k -sverilog tb.sv
vcs -R tb
mem[0]= b1000000000011010 = d32794
mem[1]= b0000000000011010 = d   26
mem[2]= b1000000000011010 = d32794
mem[3]= b1000000000011010 = d32794
mem[4]= b1000000000011010 = d32794
mem[5]= b0000000000011010 = d   26

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