judith_113 Posted November 11, 2014 Report Share Posted November 11, 2014 Hi UVM experts, I am working on a testbench to verify register behavior and came a cross an issue with W0CRS register fields with reset value of 1. Please correct me if i am wrong here. A 3-bit register field of type W0CRS with default value 3'b101. W0CRS states "W: 1/0 no effect on/clears matching bit, R: sets all bits" tx_byte_bus.configure(this, 3, 0, "W0CRS", 0, `UVM_REG_DATA_WIDTH'h00000005, 1, 1, 1); and my testcase does the following transactions to verify the register: after system reset and regModel.reset (reset all mirrored values to their default) -> write all 1's -> then followed by a read -> then followed by a 2nd read I expected the first read return 3'b101 as W0CRS shouldn't change m_value after write-all-1's is done, but the test failed with an uvm_error complaining the mirrored value is 3'b000, not match DUT value 3'b101. - if I update the default value to all 0's in both DUT and UVM_REG file, then test passed - if I udpate the default value to all 1's in both DUT and UVM_REG file, then test failed with the same error. Is this a bug with W0CRS register? thanks, Judy Quote Link to comment Share on other sites More sharing options...
tudor.timi Posted November 11, 2014 Report Share Posted November 11, 2014 This does seem a bit problematic. Could you pepper some calls to get_mirrored_value() inside your code? After reset and after each read call this method on the register that contains this field and print the returned value. I'd be curious to see if what gets returned is what we expect. Quote Link to comment Share on other sites More sharing options...
judith_113 Posted November 13, 2014 Author Report Share Posted November 13, 2014 Hi Tudor, Thank you for your suggestion. it was my bad. the reset() didn't actually happen as I was trying a few different things and left the line "regModel.reset()" uncommented but not saved in the sequence file. So it looked like I did "reset" but actually not. Once file is saved with regModel.reset(), the uvm_error is gone. so buttom line is for W0CRS with non-zero default value to work the first thing in body() should be regModel.reset(). thanks, Judy Quote Link to comment Share on other sites More sharing options...
tudor.timi Posted November 14, 2014 Report Share Posted November 14, 2014 Hi Judy, I think an even better way of doing it is to call the reset() function whenever the real reset signal is asserted. Somewhere in your testbench you should hook-up these two things and you won't need to call reset() in your sequences anymore. Quote Link to comment Share on other sites More sharing options...
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