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Grabed sequence interrupts the separated access order of register

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when the register width differs from  the bus width and one register access results in a series of bus transactions,such as


using  32bit-width data bus  can access  64-register dut  by separated  two times,this  can be  interrupted by grabed


sequence,such as interrrupt sequence,  A example of   transaction_order   may be 


    A_upper( upper 32 bit of  A register,suppose higher priority  )  -----> Interrupt service sequence(may be access interrupt clear or mask  register (two times )   ----->  A_Lower( lower 32 bit of A register)


   whether  the transaction order  is corrected  or not  ?   this may cause some unright something?,thank you  :)

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