mjet08 Posted October 13, 2014 Report Share Posted October 13, 2014 i want to use my verilog module internal signal into UVM monitor and driver,how i should do that Quote Link to comment Share on other sites More sharing options...
ciroceissler Posted October 14, 2014 Report Share Posted October 14, 2014 if you want to read the signal, here is one solution: task read; wait(top.dut.internal_module.signal == 1'b1); //do something endtask: read You can use force to drive the signal: task drive; force top.dut.internal_module.signal = 1'b1; // do something release top.dut.internal_module.signal; endtask: drive Best regards, Quote Link to comment Share on other sites More sharing options...
tudor.timi Posted October 14, 2014 Report Share Posted October 14, 2014 Be aware that adding any kind of hierarchical path like that would make your driver and monitor non-reusable. It also only works with Verilog, since hierarchical paths aren't allowed in VHDL. If you want more flexibility you can go the long way of binding an interface inside the DUT and assigning that to your monitor and driver. interface whitebox_if( input logic some_signal, input logic some_other_signal ); endinterface // somewhere in your top level bind dut whitebox_if wb_if; initial uvm_config_db #(whitebox_if)::set(null, "*", dut.wb_if); This way you can reuse your components on different projects even if the path to the signal you want changes. karandeep963 1 Quote Link to comment Share on other sites More sharing options...
apfitch Posted October 14, 2014 Report Share Posted October 14, 2014 Hi Tudor, VHDL 2008 does allow hierarchical signals. However of course for use cross-language, you are at the mercy of your simulator. regards Alan P.S. bind is better of course as you say - and cross-language bind works, again subject to your simulator. Quote Link to comment Share on other sites More sharing options...
mjet08 Posted October 15, 2014 Author Report Share Posted October 15, 2014 thnx,it really helped me Quote Link to comment Share on other sites More sharing options...
marcodemi Posted September 21, 2015 Report Share Posted September 21, 2015 Be aware that adding any kind of hierarchical path like that would make your driver and monitor non-reusable. It also only works with Verilog, since hierarchical paths aren't allowed in VHDL. If you want more flexibility you can go the long way of binding an interface inside the DUT and assigning that to your monitor and driver. interface whitebox_if( input logic some_signal, input logic some_other_signal ); endinterface // somewhere in your top level bind dut whitebox_if wb_if; initial uvm_config_db #(whitebox_if)::set(null, "*", dut.wb_if); This way you can reuse your components on different projects even if the path to the signal you want changes. Hi Tudor, I have a similar problem but I do not understand the solution you proposed. If I need to read a certain internal signal, supposing this signal is "sig" inside a DUT submodule "sub 1". Where should I put that specific signal? In which way? Thank you in advance Quote Link to comment Share on other sites More sharing options...
c4brian Posted September 21, 2015 Report Share Posted September 21, 2015 interface whitebox_if( input logic sig ); endinterface module top; Dut inst_dut (...); // instantiate DUT bind inst_dut whitebox_if wb_if( sub_1.sig ); // bind interface to DUT + connect internal signals initial uvm_config_db #(virtual whitebox_if)::set(null, "*", dut.wb_if); // place (bound/buried) interface into database endmodule Then if your testbench needs the signal, just do a database "get" of the virtual interface. Quote Link to comment Share on other sites More sharing options...
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